1. Field of the Invention
The present invention relates to a field effect transistor (FET) that operates in microwave and millimeter-wave region and more particularly to an FET having a two-stage recess structure.
2. Description of the Prior Art
Recently, tertiary and quaternary mixed crystal semiconductors such as InGaAs and InGaAsP have been drawing much attention. Among them, InGaAs lattice matched to an InP substrate is regarded as an especially promising material for not only optical devices but also various kinds of FETs. As a consequence, FETs utilizing a two-dimensional electron gas (2DEG) formed on heterointerfaces of InGaAs with InP or InAlAs have been particularly widely studied.
The reasons why InGaAs, in comparison with GaAs and the like, is considered highly as an electron transport device are as follows: (1) the peak value in electron drift velocities is high, (2) the electron mobilities at low electric fields are high, (3) it is easy to form ohmic contact electrodes and the contact resistances thereof are low, (4) the electron velocity overshoot is expected to take place, (5) noise owing to the valley scattering is low and (6) characteristics of the insulator-semiconductor interfaces are relatively good. And besides, that the afore-mentioned 2DEG device is realizable is one of the main factors.
At present, an FET utilizing a 2DEG system of the InAlAs/ InGaAs interface is expected as a potential high quality device for microwave and millimeter-wave application and has been investigated in various aspects. In particular, as a low noise element, effectiveness thereof has been confirmed by experiments. For example, at 94 GHz, noise figure of 1.2 dB and incidental gain of 7.2 dB at room temperature were reported by K. H. Duh et al. in IEEE Microwave and Guided Wave Letters, Vol.1, No.5, P.114-116, 1991. These results were obtained in a device fabricated from a material system lattice matched to an InP substrate. That is, the composition of In in the material system was set as In.sub.0.52 Al.sub.0.45 As/In.sub.0.53 Ga.sub.0.47 As. In this system, a 2DEG is formed in the In.sub.0.53 Ga.sub.0.47 As layer. In order to improve the device characteristics further, various attempts including the use of different In composition in an InGaAs channel layer, for example, setting higher than 0.53, as reported by G. I. Ng et al. in IEEE Electron Device Letters, Vol.10, No.3, P.114-116, 1989, have been made.
In such an InAlAs/InGaAs heterojunction FET, InGaAs is, in general, widely utilized as a 2DEG channel, of which the band gap is around 0.75 eV and smaller than that of GaAs and hence the rate of impact ionization is higher. Therefore, the breakdown voltage for a device is small in comparison with that for a GaAs heterojunction FET. For a stable device performance, the device is required to have a higher breakdown voltage and, in order to achieve this, several approaches have been made; on the one hand, new designs for the epilayer of the device, and on the other hand, the optimization of geometry around the gate, for example, through an expansion of the gate recess, have been being investigated.
Further, in the case that a high density cap layer is used, by setting the recess edge of this cap layer as far from the gate electrode as possible, an electric field generated by the applied voltage through the gate can be alleviated, which results in the lowered rate of impact ionization of channel electrons. This also contributes the reduction of the parasitic capacitance between the gate and the cap layer, leading to an increase in the power gain of the device. On the side of the source electrode, however, this causes an increase in the source resistance and therefore is counterbalanced by the degradation of characteristics.
Generally, InAlAs semiconductors have a problem of surface unstability, resulting from surface oxidation and the like. On the recess surface around the gate, electron traps to capture electrons sometimes develop, depending on the semiconductor material. In afore-mentioned InAlAs/InGaAs heterojunction FETs, InAlAs is often utilized as a Schottky layer of gate electrode, but, this InAlAs lattice matched to an InP substrate contains nearly 50% of Al so that the surface trap density due to oxidation and the like is high, often causing a problem of surface unstability.
A two-stage recess structure is a known method to stop reflecting the surface unstability on the device characteristics. This structure is fabricated by etching a cap layer to form a relatively wide recess, and forming, within this first recess, a second recess with a narrower recess width, and then forming a gate within this second recess. The surface of Schottky semiconductor by the side of the gate is, in this structure, placed higher than the position at which the gate electrode is formed. In this manner, even when surface unstability resulting from electron traps on the semiconductor surface and the like exists, the device performance are not affected.
FIG. 14 shows one example of conventional two-stage recess structures. In this structure, upon a semi-insulating InP substrate 201, an undoped InAlAs layer 202 as a buffer layer, an undoped InGaAs layer 203 as a channel layer, an undoped InAlAs layer 204 and an n-type doped InAlAs layer 205 as electron supply layers which supply carriers to the channel layer (an undoped InAlAs layer 204 may be regarded as a spacer layer), an undoped InAlAs layer 206 as a Schottky layer, and an n-type doped InGaAs layer 207 as a cap layer to have electrical contacts with electrodes, are grown in succession, and further, a first recess 209 is set through the cap layer (the n-type doped InGaAs layer 207) and then a second recess 210 is set within this first recess by removing a part of Schottky layer. On the exposed surface of the Schottky layer at the bottom of this second recess opening, a gate electrode 208a is formed and on the cap layer (the n-type doped InGaAs layer 207) a source electrode and a drain electrode are formed.
In such a conventional structure, if the source electrode and the drain electrode are made of metal materials and form non-alloy ohmic contacts without metal materials being alloyed with semiconductor layers, a discontinuity of the conduction-bands between InGaAs which is normally used for a cap layer and InAlAs which is normally used for a Schottky layer is large, thus causing a problem of high contact resistance.
As for the conventional FET which is fabricated upon a GaAs substrate, alloy-type ohmic electrodes, for which AuGe and Ni are used to form a source electrode and a drain electrode and then alloyed, are widely utilized in order to lower the contact resistance.
Yet, when alloy-type ohmic electrodes of AuGe and Ni are applied to a heterojunction FET fabricated upon an InP substrate, as pointed out by K. Onda et al. in MTT Symposium Proceedings, P. 261-264, 1994, for example, in acceleration tests carried out at around 300.degree. C., alloying progresses further and the resistance increases. Therefore, a problem of unreliability may arise in actual practical situations.
Meanwhile, in IEEE Electron Device Letters, Vol.13, P.325, 1992, it is demonstrated that, in a heterojunction FET having a single recess structure, non-alloy ohmic contacts can be formed by growing, upon an undoped InAlAs Schottky layer, cap layers which consist of an n-type InAlAs layer and an n-type InGaAs layer, overlying in succession. Nevertheless, in a two-stage recess structure using an InP substrate, non-alloy ohmic contact has not been known yet.
Further, with respect to this epi-structure, when the usual manufacturing method is applied to the two-stage recess structure, a first recess is formed through to an undoped InAlAs Schottky layer, and a second recess, with a narrower width than the first, is formed within the first recess, and then a gate electrode is formed within the second recess. But, in this structure, at the time of a first recess formation, two overlying cap layers of InGaAs and InAlAs are to be simultaneously removed, and thereby causes a problem that a sheet resistance right under the first recess may increase. Further, an undoped InAlAs Schottky layer is exposed at the bottom of the first recess so that the potential profile changes gradually from this exposed surface to the interior, which leads to another problem that the influence of the surface tends to appear on the device operation.
Further, as a method of manufacturing of a two-stage recess-type FET, it was a general practice that, a first recess with a wide opening is formed at the first stage by etching, and then a second recess with a narrower opening than the first is formed within the first recess by another etching. In this method, however, steps of exposure using photoresist, developing and etching are each required twice, which makes steps of manufacturing process rather complicated.